The ongoing miniaturization of feature sizes in semiconductor manufacturing processes has facilitated the formation of microscopic structures, i.e. structures that have feature sizes in the micron and submicron, e.g. nanometer domain, on substrates such as silicon substrates. A prime example of such a microscopic structure is a microelectromechanical system (MEMS) structure. Such structures are sometimes also referred to as micromachines.
MEMS structures can be used for a wide range of applications in different fields of technology, e.g. electronics, medicine, pharmacy and chemistry. Applications in the filed of electronics for instance include accelerometers, gyroscopes, sensors, and so on. The MEMS structures may be made from any suitable material, e.g. silicon, polymer, metals amongst others.
Typically, the MEMS structure requires a certain degree of translational freedom in order to perform its function. To this end, the MEMS structure is packaged such that the structure is located in a sealed cavity.
FIG. 1 shows a process flow of a typical state of the art MEMS structure manufacturing process including a packaging step. In step (a), a silicon substrate 10 carrying an oxide layer 12 and a patterned silicon layer 14 including resonant structures 16 is provided. In step (b), the resonator trenches are resealed with oxide 18, which is etched to provide contact regions to the underlying silicon layer 14. In step (c), a thin (e.g. 2 micron) layer 20 of silicon is deposited over the substrate stack in which micron-scale vent holes (not shown) are etched to allow HF vapor access for release of the resonant structures 16 in step (d), in which the cavities 22 each including a resonant structure 16 are formed. In step (e), a silicon encapsulation layer 24 is deposited at 950° C. followed by a CMP planarization and etching of the encapsulation layer 24 to define the electrical contacts. In step (f), oxide 26 is deposited to seal the trenches and is etched to allow the electrical contact to the underlying encapsulation layer 24, after which aluminum contacts 28 are formed in step (g) by deposition and etching.
This process flow has several drawbacks. For instance, the etching of the micrometer sized vent holes requires an additional processing step, thus adding to the cost of the overall manufacturing process. Also, to avoid contamination of the cavity containing the MEMS structure with capping material, the vent holes should not be located directly over the cavity, thus limiting the flexibility of the manufacturing process. Moreover, relatively thick capping layers are required to effectively seal the cavity, thus further adding to the cost of the manufacturing process.
In the paper “Wafer Level Encapsulation Technology for MEMS Devices using a HF-Permeable PECVD SIOC Capping Layer” by G. J. A. M. Verheijden et al. in MEMS 2008, IEEE 21st conference on Micro Electro Mechanical Systems 2008, pages 798-801, an alternative technology for the encapsulation of MEMS devices using a porous capping material is disclosed, which overcomes many of the problems associated with the process of FIG. 1.
The capping material consists of a low temperature PECVD layer of SiOC (trade name Black Diamond) and is shown to be permeable to HF vapor and H2O and therefore allows for the removal of a SiO2 sacrificial layer and the formation of a cavity underneath the capping layer, with the capping material being permeable enough to allow for the evacuation of the SiO2 reaction products. The cavity underneath the capping layer allows for high-Q operation of a MEMS resonator. A sealing layer can be deposited on the capping layer without significantly contaminating the cavity. However, it has been found that residual contamination of the cavity is difficult to avoid, especially when a sealing layer consisting of relatively small molecules is formed. In addition, there are no suitable process steps available to seal the porous layer at high temperature and low pressure, such that it is difficult to obtain a cavity with a high quality vacuum using this method.
In R. He et al., Journal of Micro-electromechanical Systems, Vol. 16, pages 462-472 (2007), a porous polysilicon cap layer is obtained over a MEMS structure by electrochemical etching of a polysilicon layer. Sealing of this layer is performed with the deposition of a further polysilicon layer or an LPCVD silicon oxide layer. The drawback of this approach is that the electrochemical etching of the polysilicon layer to obtain the porous polysilicon cannot be readily achieved in standard manufacturing tools, thus requiring an additional investment. In addition, the packaging method proposed in this paper requires the inclusion of a critical point drying step after the cavity formation for avoiding the MEMS structures sticking to the cavity walls. Furthermore, the required background pressures of the proposed sealing techniques are such that the preferable low pressure in the packaged cavity cannot be achieved.